As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin field-effect transistors (Fin FETs). In a Fin FET, the transistor channel rises above the planar substrate to form a fin structure, with a gate electrode adjacent to two side surfaces and the top surface of a channel region with a gate dielectric layer interposed between them.
In some field-effect transistors, at least part of the channel consists of 2D semiconductors formed around the fin structure. It is known that contact parasitic resistance is a limiting factor for achieving high performance in devices based on 2D materials, in particular as the device dimension becomes smaller. The contact resistance is inversely proportional to the contact area, which is expected to shrink as the device down-scaling continues. For 2D materials, the contact resistance is related to contact length corresponding to the perimeters between contact metal and the 2D material. In addition, in a FinFET design, the contact metal may need to be filled in a narrow trench, typically at high aspect ratio, which can present a process challenge. This is because the trend for the aspect ratio is to increase and for the trench opening is to decrease at more advanced technology nodes.
2D FinFET devices having 2D thin-film channels supported by 3D fin structures are known to have improved drive currents. The 2D FinFET device, however, faces similar issues, as explained above, with regard to contact resistance. Solutions are required that can efficiently reduce the contact resistance to improve overall performance, while at the same time alleviate the process challenges for making contact as the device dimension shrinks, such as the difficulty associated with metal filling in high aspect ratio trenches.